The present invention relates generally to an integrated circuit (IC) design, and more particularly to a circuit system for protecting a capacitor from electrostatic discharge (ESD).
Electrostatic discharge (ESD) often occurs in a very short period of time. Even a small amount of ESD charge can produce an extremely high voltage when the ESD current flows through an electronic device, and cause serious damages. For example, during an ESD event, a high voltage difference can be created at two ends of a capacitor and damage the dielectric layer disposed therebetween.
An ESD protection device is typically implemented in an IC for protecting the electronic devices within the IC from ESD induced damages. One of the ESD protection devices is a grounded-gate NMOS (GGNMOS) transistor. The GGNMOS transistor is typically coupled in parallel to a protected device between a voltage supply node and ground. The GGNMOS transistor has no impact on the normal operation of the protected device, as its gate is coupled to ground. During an ESD event, the GGNMOS transistor passes the ESD current thereacross due to the junction breakdown induced by the high ESD voltage. The GGNMOS transistor creates a current path for the ESD current to bypass the protected device, thereby protecting it from ESD induced damages.
While the GGNMOS transistor is effective in protecting devices manufactured by a processing technology of a 90 nm or higher generation, it cannot properly protect devices manufactured by a processing technology of a 65 nm or lower generation. For example, a capacitor manufactured by the 65 nm processing technology usually has a dielectric layer with a thickness smaller than 14 angstroms. This thin dielectric layer is very susceptible to high voltage induced damages. During an ESD event, the capacitor can be damaged before the GGNMOS transistor is triggered on. As the processing technology advances, the dielectric layer becomes thinner, and the ESD induced damage issues become increasingly serious.
Thus, what is needed is an improved ESD protection circuit that can better protect devices manufactured by the processing technology of a 65 nm or lower generation from ESD induced damages.